1. Technical Field of the Invention
The present invention relates generally to bandgap voltage reference generation circuitry realized in CMOS process. More particularly, the present invention relates to a bandgap voltage reference generator with high PSRR and low power dissipation suitable for use with a low voltage supply.
2. Description of Related Art
Reference in now made to FIG. 1 wherein there is shown a circuit diagram of a classical implementation of a bandgap voltage reference generator 10. The generator 10 includes an operational amplifier (OPAMP) 12 having a positive input 14, a negative input 16 and an output 18. A voltage divider is formed by two series connected resistors R1 and R2 which are coupled together at node Y, with node Y being connected to the negative input 16. A first end of the voltage divider is connected to the output 18 of the operational amplifier 12. A second end of the voltage divider is connected to the emitter of a bi-polar transistor Q2. The collector and base of the transistor Q2 are connected to a ground reference. A resistor R3 is coupled between the output 18 of the operational amplifier 12 and node X, with node X being connected to the positive input 14. Node X is further connected to the emitter of a bi-polar transistor Q1. The collector and base of the transistor Q1 are connected to a ground reference, such that the bases of the transistors Q1 and Q2 are connected together.
The OPAMP 12 is needed to make the voltage at nodes X and Y equal and stable. In addition to this, an improvement in PSRR with the OPAMP allows for its wide use in bandgap circuits. In a normal application, the OPAMP is just a basic differential input operational amplifier. However, to improve PSRR in low voltage applications, a high performance with high gain and high speed and low-offset OPAMP is desired. This results in a bandgap circuit that is more complex with a higher power dissipation. Such a circuit is not well suited for use in signal processing applications such as in a data converter.
Given the foregoing, there is an interest in the use of OPAMP-less bandgap generators. However, such circuits are typically not suitable for signal processing applications for a number of reasons.
Reference is now made to FIGS. 2 and 3 which illustrate, respectively, a simple and a cascode OPAMP-less bandgap voltage reference generator circuit known in the prior art.
In FIG. 2, bipolar transistors Q1 and Q2 are connected as in FIG. 1 with their collectors and bases coupled to the ground reference voltage. With respect to the emitter of transistor Q1, it is connected to a supply reference voltage Vdd through the series-connected source-drain circuits of MOS transistors M1 and M3 (where M1 is an n-channel device and M3 is a p-channel device). The gate of transistor M1 is connected to the drain of transistor M1. With respect to the emitter of transistor Q2, it is connected to the supply reference voltage Vdd through the series-connected source-drain circuits of MOS transistors M2 and M4 (where M2 is an n-channel device and M4 is a p-channel device) and series connected resistor R1. The resistor R1 is coupled between the emitter of transistor Q2 and the source of transistor M2. The gate of transistor M4 is connected to the drain of transistor M4. Additionally, the gate of transistor M4 is connected to the gate of transistor M3, while the gate of transistor M2 is connected to the gate of transistor M1. A third bipolar transistor Q3 is provided with its collector and base coupled to the ground reference voltage. With respect to the emitter of transistor Q3, it is connected to the supply reference voltage Vdd through the series-connected source-drain circuit of p-channel MOS transistor M5 and resistor R2. The resistor R2 is coupled between the emitter of transistor Q3 and the drain of transistor M5, with the bandgap output voltage Vbg being taken at the drain of transistor M5. The gate of transistor M5 is connected to the gates of transistors M3 and M4.
In FIG. 3, bipolar transistors Q1 and Q2 are connected as in FIG. 1 with their collectors and bases coupled to the ground reference voltage. With respect to the emitter of transistor Q1, it is connected to the supply reference voltage Vdd through the series-connected source-drain circuits of MOS transistors M1, M1a, M3a and M3 (where M1/M1a are n-channel devices and M3a/M3 are p-channel devices). The gate of transistor M1 is connected to the drains of transistors M1a and M3a. The gate of transistor M1a receives a bias voltage Vb2, and the gate of transistor M3a receives a bias voltage Vb1. With respect to the emitter of transistor Q2, it is connected to the supply reference voltage Vdd through the series-connected source-drain circuits of MOS transistors M2, M2a, M4a and M4 (where M2/M2a are n-channel devices and M4a/M4 are p-channel devices) and series connected resistor R1. The resistor R1 is coupled between the emitter of transistor Q2 and the source of transistor M2. The gate of transistor M4 is connected to the drains of transistor M2a and M4a. Additionally, the gate of transistor M4 is connected to the gate of transistor M3, while the gate of transistor M2 is connected to the gate of transistor M1. The gate of transistor M2a also receives the bias voltage Vb2, and the gate of transistor M4a also receives the bias voltage Vb1. A third bipolar transistor Q3 is provided with its collector and base coupled to the ground reference voltage. With respect to the emitter of transistor Q3, it is connected to the supply reference voltage Vdd through the series-connected source-drain circuits of p-channel MOS transistors M5 and M5a and resistor R2. The resistor R2 is coupled between the emitter of transistor Q3 and the drain of transistor M5a, with the bandgap output voltage Vbg being taken at the drain of transistor M5a. The gate of transistor M5a also receives the bias voltage Vb1. The gate of transistor M5 is connected to the gates of transistors M3 and M4.
The bandgap voltage Vbg is (equation 1):
  Vbg  =            Vbe      ⁢                          ⁢      3        +                            R          ⁢                                          ⁢          2                          R          ⁢                                          ⁢          1                    ⁢              V        T            ⁢      ln      ⁢                          ⁢      N      wherein N is the aspect ratio of Q2 and Q1.
The effective PSRR is expressed as (equation 2):
  PSRR  =                    Δ        ⁢                                  ⁢        Vin                    Δ        ⁢                                  ⁢        Vbg              =                            Z          gnd                +                  Z                                    i              ⁢                                                          ⁢              n                        ⁢                                                                            Z        gnd            wherein ΔVbg and ΔVin refer to changes in the bandgap reference voltage and the input supply voltage Vdd, respectively, while Zgnd and Zin represent the effective impedance from the reference to the ground node and to the input supply voltage, respectively.
Obviously, Zin is only ro5 and not large enough to achieve high PSRR in FIG. 2. The PSRR is largely improved in FIG. 3 since the cascode is being used to increase the impedance from the reference voltage to the input supply. In this case, it is noted (equation 3):Zin≈gm5aro5ro5a 
Other techniques to improve PSRR for OPAMP-less bandgap, such as a regulated cascade technique, also can be adopted, but it is difficult to realize. Even though the PSRR is high for the techniques of FIGS. 2 and 3, it is not high enough for use in a data converter or other high performance application.
In summary, a number of drawbacks have been noted with respect to the traditional bandgap circuit designs for use in data converter and other high performance circuits: 1) the requirements for the OPAMP (see, FIG. 1) are high for an OPAMP bandgap circuit and the dissipation area is increased; and 2) the PSRR is not high enough for OPAMP-less bandgap designs. Even high PSRR OPAMP-less bandgap circuits have drawbacks since their minimum supply voltage is too high and the circuits are not compatible with the standard CMOS process.
A need accordingly exists for a bandgap circuit which overcomes the foregoing drawbacks and is compatible with the standard CMOS process. The circuit should possess high PSRR and a low temperature coefficient. The circuit should preferably be OPAMP-less so as to minimize dissipation. The circuit should also be compatible with low supply voltages.